Arithmetic Built In Self Test for Embedded Systems

Janusz Rajski, Jerzy Tyszer, "Arithmetic Built-In Self-Test for Embedded Systems"

Prentice Hall | 1997-10 | ISBN: 0137564384 | 268 pages | PDF | 5.3 MB

Arithmetic Built-In Self-Test for Embedded Systems offers a thorough treatment of the important issues in software-based built-in self-test for systems with embedded processors. Fundamental concepts are illustrated with practical scenarios for test generation, test application, and test response compaction. Arithmetic Built-In Self-Test for Embedded Systems uses an approach to cutting-edge technology that will be of interest to hardware and embedded system designers, test and design engineers, and researchers working on IC/core testing. It is also appropriate for graduate-level design courses. An introductory chapter provides a comprehensive tutorial covering the most relevant DFT and BIST techniques.

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